mirror of
https://github.com/momo5502/hypervisor.git
synced 2025-04-19 21:52:55 +00:00
More cleanup
This commit is contained in:
parent
0ea1ae9643
commit
6052d25070
@ -102,7 +102,7 @@ void hypervisor::enable()
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volatile long failures = 0;
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volatile long failures = 0;
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thread::dispatch_on_all_cores([&]()
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thread::dispatch_on_all_cores([&]()
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{
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{
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if(!this->try_enable_core(cr3))
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if (!this->try_enable_core(cr3))
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{
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{
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InterlockedIncrement(&failures);
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InterlockedIncrement(&failures);
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}
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}
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@ -126,7 +126,8 @@ bool hypervisor::try_enable_core(const uint64_t system_directory_table_base)
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{
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{
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debug_log("Failed to enable hypervisor on core %d: %s\n", thread::get_processor_index(), e.what());
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debug_log("Failed to enable hypervisor on core %d: %s\n", thread::get_processor_index(), e.what());
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return false;
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return false;
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}catch (...)
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}
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catch (...)
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{
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{
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debug_log("Failed to enable hypervisor on core %d.\n", thread::get_processor_index());
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debug_log("Failed to enable hypervisor on core %d.\n", thread::get_processor_index());
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return false;
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return false;
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@ -192,7 +193,6 @@ ShvVmxLaunch(
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VOID ShvVmxMtrrInitialize(vmx::vm_state* VpData)
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VOID ShvVmxMtrrInitialize(vmx::vm_state* VpData)
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{
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{
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UINT32 i;
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ia32_mtrr_capabilities_register mtrrCapabilities;
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ia32_mtrr_capabilities_register mtrrCapabilities;
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ia32_mtrr_physbase_register mtrrBase;
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ia32_mtrr_physbase_register mtrrBase;
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ia32_mtrr_physmask_register mtrrMask;
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ia32_mtrr_physmask_register mtrrMask;
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@ -206,7 +206,7 @@ VOID ShvVmxMtrrInitialize(vmx::vm_state* VpData)
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//
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//
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// Iterate over each variable MTRR
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// Iterate over each variable MTRR
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//
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//
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for (i = 0; i < mtrrCapabilities.variable_range_count; i++)
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for (auto i = 0u; i < mtrrCapabilities.variable_range_count; i++)
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{
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{
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//
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//
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// Capture the value
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// Capture the value
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@ -245,12 +245,10 @@ ShvVmxMtrrAdjustEffectiveMemoryType(
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_In_ UINT32 CandidateMemoryType
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_In_ UINT32 CandidateMemoryType
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)
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)
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{
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{
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UINT32 i;
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//
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//
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// Loop each MTRR range
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// Loop each MTRR range
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//
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//
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for (i = 0; i < sizeof(VpData->mtrr_data) / sizeof(VpData->mtrr_data[0]); i++)
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for (auto i = 0u; i < sizeof(VpData->mtrr_data) / sizeof(VpData->mtrr_data[0]); i++)
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{
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{
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//
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//
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// Check if it's active
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// Check if it's active
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@ -283,9 +281,9 @@ void ShvVmxEptInitialize(vmx::vm_state* VpData)
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//
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//
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// Fill out the EPML4E which covers the first 512GB of RAM
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// Fill out the EPML4E which covers the first 512GB of RAM
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//
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//
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VpData->epml4[0].read = 1;
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VpData->epml4[0].read_access = 1;
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VpData->epml4[0].write = 1;
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VpData->epml4[0].write_access = 1;
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VpData->epml4[0].execute = 1;
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VpData->epml4[0].execute_access = 1;
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VpData->epml4[0].page_frame_number = memory::get_physical_address(&VpData->epdpt) /
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VpData->epml4[0].page_frame_number = memory::get_physical_address(&VpData->epdpt) /
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PAGE_SIZE;
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PAGE_SIZE;
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@ -453,91 +451,10 @@ ShvVmxEnterRootModeOnVp(vmx::vm_state* VpData)
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return TRUE;
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return TRUE;
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}
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}
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typedef struct _VMX_GDTENTRY64
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{
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UINT64 Base;
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UINT32 Limit;
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union
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{
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struct
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{
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UINT8 Flags1;
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UINT8 Flags2;
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UINT8 Flags3;
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UINT8 Flags4;
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} Bytes;
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struct
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{
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UINT16 SegmentType : 4;
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UINT16 DescriptorType : 1;
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UINT16 Dpl : 2;
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UINT16 Present : 1;
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UINT16 Reserved : 4;
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UINT16 System : 1;
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UINT16 LongMode : 1;
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UINT16 DefaultBig : 1;
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UINT16 Granularity : 1;
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UINT16 Unusable : 1;
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UINT16 Reserved2 : 15;
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} Bits;
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UINT32 AccessRights;
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};
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UINT16 Selector;
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} VMX_GDTENTRY64, *PVMX_GDTENTRY64;
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typedef union _KGDTENTRY64
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{
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struct
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{
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UINT16 LimitLow;
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UINT16 BaseLow;
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union
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{
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struct
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{
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UINT8 BaseMiddle;
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UINT8 Flags1;
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UINT8 Flags2;
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UINT8 BaseHigh;
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} Bytes;
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struct
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{
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UINT32 BaseMiddle : 8;
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UINT32 Type : 5;
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UINT32 Dpl : 2;
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UINT32 Present : 1;
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UINT32 LimitHigh : 4;
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UINT32 System : 1;
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UINT32 LongMode : 1;
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UINT32 DefaultBig : 1;
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UINT32 Granularity : 1;
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UINT32 BaseHigh : 8;
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} Bits;
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};
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UINT32 BaseUpper;
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UINT32 MustBeZero;
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};
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struct
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{
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INT64 DataLow;
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INT64 DataHigh;
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};
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} KGDTENTRY64, *PKGDTENTRY64;
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VOID
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VOID
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ShvUtilConvertGdtEntry(
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ShvUtilConvertGdtEntry(
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_In_ VOID* GdtBase,
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_In_ uint64_t GdtBase,
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_In_ UINT16 Selector,
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_In_ UINT16 Selector,
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_Out_ PVMX_GDTENTRY64 VmxGdtEntry
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_Out_ PVMX_GDTENTRY64 VmxGdtEntry
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)
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)
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@ -560,7 +477,7 @@ ShvUtilConvertGdtEntry(
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//
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//
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// Read the GDT entry at the given selector, masking out the RPL bits.
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// Read the GDT entry at the given selector, masking out the RPL bits.
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//
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//
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gdtEntry = (PKGDTENTRY64)((uintptr_t)GdtBase + (Selector & ~SEGMENT_ACCESS_RIGHTS_DESCRIPTOR_PRIVILEGE_LEVEL_MASK));
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gdtEntry = (PKGDTENTRY64)(GdtBase + (Selector & ~SEGMENT_ACCESS_RIGHTS_DESCRIPTOR_PRIVILEGE_LEVEL_MASK));
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//
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//
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// Write the selector directly
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// Write the selector directly
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@ -1072,7 +989,7 @@ void ShvVmxSetupVmcsForVp(vmx::vm_state* VpData)
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//
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//
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// Load the CS Segment (Ring 0 Code)
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// Load the CS Segment (Ring 0 Code)
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//
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//
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ShvUtilConvertGdtEntry(state->gdtr.base, context->SegCs, &vmxGdtEntry);
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ShvUtilConvertGdtEntry(state->gdtr.base_address, context->SegCs, &vmxGdtEntry);
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__vmx_vmwrite(VMCS_GUEST_CS_SELECTOR, vmxGdtEntry.Selector);
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__vmx_vmwrite(VMCS_GUEST_CS_SELECTOR, vmxGdtEntry.Selector);
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__vmx_vmwrite(VMCS_GUEST_CS_LIMIT, vmxGdtEntry.Limit);
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__vmx_vmwrite(VMCS_GUEST_CS_LIMIT, vmxGdtEntry.Limit);
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__vmx_vmwrite(VMCS_GUEST_CS_ACCESS_RIGHTS, vmxGdtEntry.AccessRights);
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__vmx_vmwrite(VMCS_GUEST_CS_ACCESS_RIGHTS, vmxGdtEntry.AccessRights);
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@ -1082,7 +999,7 @@ void ShvVmxSetupVmcsForVp(vmx::vm_state* VpData)
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//
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//
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// Load the SS Segment (Ring 0 Data)
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// Load the SS Segment (Ring 0 Data)
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//
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//
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ShvUtilConvertGdtEntry(state->gdtr.base, context->SegSs, &vmxGdtEntry);
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ShvUtilConvertGdtEntry(state->gdtr.base_address, context->SegSs, &vmxGdtEntry);
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__vmx_vmwrite(VMCS_GUEST_SS_SELECTOR, vmxGdtEntry.Selector);
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__vmx_vmwrite(VMCS_GUEST_SS_SELECTOR, vmxGdtEntry.Selector);
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__vmx_vmwrite(VMCS_GUEST_SS_LIMIT, vmxGdtEntry.Limit);
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__vmx_vmwrite(VMCS_GUEST_SS_LIMIT, vmxGdtEntry.Limit);
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__vmx_vmwrite(VMCS_GUEST_SS_ACCESS_RIGHTS, vmxGdtEntry.AccessRights);
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__vmx_vmwrite(VMCS_GUEST_SS_ACCESS_RIGHTS, vmxGdtEntry.AccessRights);
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@ -1092,7 +1009,7 @@ void ShvVmxSetupVmcsForVp(vmx::vm_state* VpData)
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//
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//
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// Load the DS Segment (Ring 3 Data)
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// Load the DS Segment (Ring 3 Data)
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//
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//
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ShvUtilConvertGdtEntry(state->gdtr.base, context->SegDs, &vmxGdtEntry);
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ShvUtilConvertGdtEntry(state->gdtr.base_address, context->SegDs, &vmxGdtEntry);
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__vmx_vmwrite(VMCS_GUEST_DS_SELECTOR, vmxGdtEntry.Selector);
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__vmx_vmwrite(VMCS_GUEST_DS_SELECTOR, vmxGdtEntry.Selector);
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__vmx_vmwrite(VMCS_GUEST_DS_LIMIT, vmxGdtEntry.Limit);
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__vmx_vmwrite(VMCS_GUEST_DS_LIMIT, vmxGdtEntry.Limit);
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__vmx_vmwrite(VMCS_GUEST_DS_ACCESS_RIGHTS, vmxGdtEntry.AccessRights);
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__vmx_vmwrite(VMCS_GUEST_DS_ACCESS_RIGHTS, vmxGdtEntry.AccessRights);
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@ -1102,7 +1019,7 @@ void ShvVmxSetupVmcsForVp(vmx::vm_state* VpData)
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//
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//
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// Load the ES Segment (Ring 3 Data)
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// Load the ES Segment (Ring 3 Data)
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//
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//
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ShvUtilConvertGdtEntry(state->gdtr.base, context->SegEs, &vmxGdtEntry);
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ShvUtilConvertGdtEntry(state->gdtr.base_address, context->SegEs, &vmxGdtEntry);
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__vmx_vmwrite(VMCS_GUEST_ES_SELECTOR, vmxGdtEntry.Selector);
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__vmx_vmwrite(VMCS_GUEST_ES_SELECTOR, vmxGdtEntry.Selector);
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__vmx_vmwrite(VMCS_GUEST_ES_LIMIT, vmxGdtEntry.Limit);
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__vmx_vmwrite(VMCS_GUEST_ES_LIMIT, vmxGdtEntry.Limit);
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__vmx_vmwrite(VMCS_GUEST_ES_ACCESS_RIGHTS, vmxGdtEntry.AccessRights);
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__vmx_vmwrite(VMCS_GUEST_ES_ACCESS_RIGHTS, vmxGdtEntry.AccessRights);
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@ -1112,7 +1029,7 @@ void ShvVmxSetupVmcsForVp(vmx::vm_state* VpData)
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//
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//
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// Load the FS Segment (Ring 3 Compatibility-Mode TEB)
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// Load the FS Segment (Ring 3 Compatibility-Mode TEB)
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//
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//
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ShvUtilConvertGdtEntry(state->gdtr.base, context->SegFs, &vmxGdtEntry);
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ShvUtilConvertGdtEntry(state->gdtr.base_address, context->SegFs, &vmxGdtEntry);
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__vmx_vmwrite(VMCS_GUEST_FS_SELECTOR, vmxGdtEntry.Selector);
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__vmx_vmwrite(VMCS_GUEST_FS_SELECTOR, vmxGdtEntry.Selector);
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__vmx_vmwrite(VMCS_GUEST_FS_LIMIT, vmxGdtEntry.Limit);
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__vmx_vmwrite(VMCS_GUEST_FS_LIMIT, vmxGdtEntry.Limit);
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__vmx_vmwrite(VMCS_GUEST_FS_ACCESS_RIGHTS, vmxGdtEntry.AccessRights);
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__vmx_vmwrite(VMCS_GUEST_FS_ACCESS_RIGHTS, vmxGdtEntry.AccessRights);
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@ -1123,7 +1040,7 @@ void ShvVmxSetupVmcsForVp(vmx::vm_state* VpData)
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//
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//
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// Load the GS Segment (Ring 3 Data if in Compatibility-Mode, MSR-based in Long Mode)
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// Load the GS Segment (Ring 3 Data if in Compatibility-Mode, MSR-based in Long Mode)
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//
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//
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ShvUtilConvertGdtEntry(state->gdtr.base, context->SegGs, &vmxGdtEntry);
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ShvUtilConvertGdtEntry(state->gdtr.base_address, context->SegGs, &vmxGdtEntry);
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__vmx_vmwrite(VMCS_GUEST_GS_SELECTOR, vmxGdtEntry.Selector);
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__vmx_vmwrite(VMCS_GUEST_GS_SELECTOR, vmxGdtEntry.Selector);
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__vmx_vmwrite(VMCS_GUEST_GS_LIMIT, vmxGdtEntry.Limit);
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__vmx_vmwrite(VMCS_GUEST_GS_LIMIT, vmxGdtEntry.Limit);
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__vmx_vmwrite(VMCS_GUEST_GS_ACCESS_RIGHTS, vmxGdtEntry.AccessRights);
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__vmx_vmwrite(VMCS_GUEST_GS_ACCESS_RIGHTS, vmxGdtEntry.AccessRights);
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@ -1134,7 +1051,7 @@ void ShvVmxSetupVmcsForVp(vmx::vm_state* VpData)
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//
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//
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// Load the Task Register (Ring 0 TSS)
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// Load the Task Register (Ring 0 TSS)
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//
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//
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ShvUtilConvertGdtEntry(state->gdtr.base, state->tr, &vmxGdtEntry);
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ShvUtilConvertGdtEntry(state->gdtr.base_address, state->tr, &vmxGdtEntry);
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__vmx_vmwrite(VMCS_GUEST_TR_SELECTOR, vmxGdtEntry.Selector);
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__vmx_vmwrite(VMCS_GUEST_TR_SELECTOR, vmxGdtEntry.Selector);
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__vmx_vmwrite(VMCS_GUEST_TR_LIMIT, vmxGdtEntry.Limit);
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__vmx_vmwrite(VMCS_GUEST_TR_LIMIT, vmxGdtEntry.Limit);
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__vmx_vmwrite(VMCS_GUEST_TR_ACCESS_RIGHTS, vmxGdtEntry.AccessRights);
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__vmx_vmwrite(VMCS_GUEST_TR_ACCESS_RIGHTS, vmxGdtEntry.AccessRights);
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@ -1145,7 +1062,7 @@ void ShvVmxSetupVmcsForVp(vmx::vm_state* VpData)
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//
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//
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// Load the Local Descriptor Table (Ring 0 LDT on Redstone)
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// Load the Local Descriptor Table (Ring 0 LDT on Redstone)
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//
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//
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ShvUtilConvertGdtEntry(state->gdtr.base, state->ldtr, &vmxGdtEntry);
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ShvUtilConvertGdtEntry(state->gdtr.base_address, state->ldtr, &vmxGdtEntry);
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__vmx_vmwrite(VMCS_GUEST_LDTR_SELECTOR, vmxGdtEntry.Selector);
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__vmx_vmwrite(VMCS_GUEST_LDTR_SELECTOR, vmxGdtEntry.Selector);
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__vmx_vmwrite(VMCS_GUEST_LDTR_LIMIT, vmxGdtEntry.Limit);
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__vmx_vmwrite(VMCS_GUEST_LDTR_LIMIT, vmxGdtEntry.Limit);
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__vmx_vmwrite(VMCS_GUEST_LDTR_ACCESS_RIGHTS, vmxGdtEntry.AccessRights);
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__vmx_vmwrite(VMCS_GUEST_LDTR_ACCESS_RIGHTS, vmxGdtEntry.AccessRights);
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@ -1154,16 +1071,16 @@ void ShvVmxSetupVmcsForVp(vmx::vm_state* VpData)
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//
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//
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// Now load the GDT itself
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// Now load the GDT itself
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//
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//
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__vmx_vmwrite(VMCS_GUEST_GDTR_BASE, (uintptr_t)state->gdtr.base);
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__vmx_vmwrite(VMCS_GUEST_GDTR_BASE, state->gdtr.base_address);
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__vmx_vmwrite(VMCS_GUEST_GDTR_LIMIT, state->gdtr.limit);
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__vmx_vmwrite(VMCS_GUEST_GDTR_LIMIT, state->gdtr.limit);
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__vmx_vmwrite(VMCS_HOST_GDTR_BASE, (uintptr_t)state->gdtr.base);
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__vmx_vmwrite(VMCS_HOST_GDTR_BASE, state->gdtr.base_address);
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//
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//
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// And then the IDT
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// And then the IDT
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//
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//
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__vmx_vmwrite(VMCS_GUEST_IDTR_BASE, (uintptr_t)state->idtr.base);
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__vmx_vmwrite(VMCS_GUEST_IDTR_BASE, state->idtr.base_address);
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__vmx_vmwrite(VMCS_GUEST_IDTR_LIMIT, state->idtr.limit);
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__vmx_vmwrite(VMCS_GUEST_IDTR_LIMIT, state->idtr.limit);
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__vmx_vmwrite(VMCS_HOST_IDTR_BASE, (uintptr_t)state->idtr.base);
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__vmx_vmwrite(VMCS_HOST_IDTR_BASE, state->idtr.base_address);
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//
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//
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// Load CR0
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// Load CR0
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@ -13,17 +13,11 @@ namespace thread
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void* data{};
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void* data{};
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};
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};
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void dispatch_callback(const void* context)
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_Function_class_(KDEFERRED_ROUTINE)
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void NTAPI callback_dispatcher(struct _KDPC* /*Dpc*/,
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const PVOID param,
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const PVOID arg1,
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const PVOID arg2)
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{
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{
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try
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try
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{
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{
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const auto* const data = static_cast<dispatch_data*>(param);
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const auto* const data = static_cast<const dispatch_data*>(context);
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data->callback(data->data);
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data->callback(data->data);
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}
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}
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catch (std::exception& e)
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catch (std::exception& e)
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@ -34,6 +28,17 @@ namespace thread
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{
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{
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debug_log("Unknown exception during dpc on core %d\n", get_processor_index());
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debug_log("Unknown exception during dpc on core %d\n", get_processor_index());
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}
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}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
_Function_class_(KDEFERRED_ROUTINE)
|
||||||
|
|
||||||
|
void NTAPI callback_dispatcher(struct _KDPC* /*Dpc*/,
|
||||||
|
const PVOID param,
|
||||||
|
const PVOID arg1,
|
||||||
|
const PVOID arg2)
|
||||||
|
{
|
||||||
|
dispatch_callback(param);
|
||||||
|
|
||||||
KeSignalCallDpcSynchronize(arg2);
|
KeSignalCallDpcSynchronize(arg2);
|
||||||
KeSignalCallDpcDone(arg1);
|
KeSignalCallDpcDone(arg1);
|
||||||
@ -51,19 +56,7 @@ namespace thread
|
|||||||
{
|
{
|
||||||
if (i == current_cpu)
|
if (i == current_cpu)
|
||||||
{
|
{
|
||||||
try
|
dispatch_callback(param);
|
||||||
{
|
|
||||||
const auto* const data = static_cast<dispatch_data*>(param);
|
|
||||||
data->callback(data->data);
|
|
||||||
}
|
|
||||||
catch (std::exception& e)
|
|
||||||
{
|
|
||||||
debug_log("Exception during dpc on core %d: %s\n", get_processor_index(), e.what());
|
|
||||||
}
|
|
||||||
catch (...)
|
|
||||||
{
|
|
||||||
debug_log("Unknown exception during dpc on core %d\n", get_processor_index());
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
KeSignalCallDpcSynchronize(arg2);
|
KeSignalCallDpcSynchronize(arg2);
|
||||||
|
@ -9,36 +9,6 @@ namespace vmx
|
|||||||
uint8_t data[PAGE_SIZE - 8];
|
uint8_t data[PAGE_SIZE - 8];
|
||||||
};
|
};
|
||||||
|
|
||||||
struct epml4e
|
|
||||||
{
|
|
||||||
union
|
|
||||||
{
|
|
||||||
struct
|
|
||||||
{
|
|
||||||
uint64_t read : 1;
|
|
||||||
uint64_t write : 1;
|
|
||||||
uint64_t execute : 1;
|
|
||||||
uint64_t reserved : 5;
|
|
||||||
uint64_t accessed : 1;
|
|
||||||
uint64_t software_use : 1;
|
|
||||||
uint64_t user_mode_execute : 1;
|
|
||||||
uint64_t software_use2 : 1;
|
|
||||||
uint64_t page_frame_number : 36;
|
|
||||||
uint64_t reserved_high : 4;
|
|
||||||
uint64_t software_use_high : 12;
|
|
||||||
};
|
|
||||||
|
|
||||||
uint64_t full;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
struct kdescriptor
|
|
||||||
{
|
|
||||||
uint16_t pad[3];
|
|
||||||
uint16_t limit;
|
|
||||||
void* base;
|
|
||||||
};
|
|
||||||
|
|
||||||
struct special_registers
|
struct special_registers
|
||||||
{
|
{
|
||||||
uint64_t cr0;
|
uint64_t cr0;
|
||||||
@ -49,8 +19,8 @@ namespace vmx
|
|||||||
uint16_t ldtr;
|
uint16_t ldtr;
|
||||||
uint64_t debug_control;
|
uint64_t debug_control;
|
||||||
uint64_t kernel_dr7;
|
uint64_t kernel_dr7;
|
||||||
kdescriptor idtr;
|
segment_descriptor_register_64 idtr;
|
||||||
kdescriptor gdtr;
|
segment_descriptor_register_64 gdtr;
|
||||||
};
|
};
|
||||||
|
|
||||||
struct mtrr_range
|
struct mtrr_range
|
||||||
@ -85,7 +55,7 @@ namespace vmx
|
|||||||
};
|
};
|
||||||
|
|
||||||
DECLSPEC_PAGE_ALIGN uint8_t msr_bitmap[PAGE_SIZE]{};
|
DECLSPEC_PAGE_ALIGN uint8_t msr_bitmap[PAGE_SIZE]{};
|
||||||
DECLSPEC_PAGE_ALIGN epml4e epml4[EPT_PML4E_ENTRY_COUNT]{};
|
DECLSPEC_PAGE_ALIGN ept_pml4 epml4[EPT_PML4E_ENTRY_COUNT]{};
|
||||||
DECLSPEC_PAGE_ALIGN epdpte epdpt[EPT_PDPTE_ENTRY_COUNT]{};
|
DECLSPEC_PAGE_ALIGN epdpte epdpt[EPT_PDPTE_ENTRY_COUNT]{};
|
||||||
DECLSPEC_PAGE_ALIGN epde_2mb epde[EPT_PDPTE_ENTRY_COUNT][EPT_PDE_ENTRY_COUNT]{};
|
DECLSPEC_PAGE_ALIGN epde_2mb epde[EPT_PDPTE_ENTRY_COUNT][EPT_PDE_ENTRY_COUNT]{};
|
||||||
|
|
||||||
@ -93,3 +63,86 @@ namespace vmx
|
|||||||
DECLSPEC_PAGE_ALIGN vmcs vmcs{};
|
DECLSPEC_PAGE_ALIGN vmcs vmcs{};
|
||||||
};
|
};
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
typedef struct _VMX_GDTENTRY64
|
||||||
|
{
|
||||||
|
UINT64 Base;
|
||||||
|
UINT32 Limit;
|
||||||
|
|
||||||
|
union
|
||||||
|
{
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
UINT8 Flags1;
|
||||||
|
UINT8 Flags2;
|
||||||
|
UINT8 Flags3;
|
||||||
|
UINT8 Flags4;
|
||||||
|
} Bytes;
|
||||||
|
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
UINT16 SegmentType : 4;
|
||||||
|
UINT16 DescriptorType : 1;
|
||||||
|
UINT16 Dpl : 2;
|
||||||
|
UINT16 Present : 1;
|
||||||
|
|
||||||
|
UINT16 Reserved : 4;
|
||||||
|
UINT16 System : 1;
|
||||||
|
UINT16 LongMode : 1;
|
||||||
|
UINT16 DefaultBig : 1;
|
||||||
|
UINT16 Granularity : 1;
|
||||||
|
|
||||||
|
UINT16 Unusable : 1;
|
||||||
|
UINT16 Reserved2 : 15;
|
||||||
|
} Bits;
|
||||||
|
|
||||||
|
UINT32 AccessRights;
|
||||||
|
};
|
||||||
|
|
||||||
|
UINT16 Selector;
|
||||||
|
} VMX_GDTENTRY64, *PVMX_GDTENTRY64;
|
||||||
|
|
||||||
|
|
||||||
|
typedef union _KGDTENTRY64
|
||||||
|
{
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
UINT16 LimitLow;
|
||||||
|
UINT16 BaseLow;
|
||||||
|
|
||||||
|
union
|
||||||
|
{
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
UINT8 BaseMiddle;
|
||||||
|
UINT8 Flags1;
|
||||||
|
UINT8 Flags2;
|
||||||
|
UINT8 BaseHigh;
|
||||||
|
} Bytes;
|
||||||
|
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
UINT32 BaseMiddle : 8;
|
||||||
|
UINT32 Type : 5;
|
||||||
|
UINT32 Dpl : 2;
|
||||||
|
UINT32 Present : 1;
|
||||||
|
UINT32 LimitHigh : 4;
|
||||||
|
UINT32 System : 1;
|
||||||
|
UINT32 LongMode : 1;
|
||||||
|
UINT32 DefaultBig : 1;
|
||||||
|
UINT32 Granularity : 1;
|
||||||
|
UINT32 BaseHigh : 8;
|
||||||
|
} Bits;
|
||||||
|
};
|
||||||
|
|
||||||
|
UINT32 BaseUpper;
|
||||||
|
UINT32 MustBeZero;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
INT64 DataLow;
|
||||||
|
INT64 DataHigh;
|
||||||
|
};
|
||||||
|
} KGDTENTRY64, *PKGDTENTRY64;
|
Loading…
x
Reference in New Issue
Block a user