Allow syntax cpl a

man/gbz80.7

@@ -11,16 +11,28 @@ This is the list of opcodes supported by
 .Xr rgbasm 1 ,
 including a short description, the number of bytes needed to encode them and the number of CPU cycles at 1MHz (or 2MHz in GBC dual speed mode) needed to complete them.
 .Pp
-Note: All arithmetic/logic operations that use register
+Note: All arithmetic/logic instructions that use register
 .Sy A
-as destination can omit the destination as it is assumed to be register
+as a destination can omit the destination, since it is assumed to be register
 .Sy A
 by default.
-The following two lines have the same effect:
+So the following two lines have the same effect:
 .Bd -literal -offset indent
 OR A,B
 OR B
 .Ed
+.Pp
+Furthermore, the
+.Sy CPL
+instruction can take an optional
+.Sy A
+destination, since it can only be register
+.Sy A .
+So the following two lines have the same effect:
+.Bd -literal -offset indent
+CPL
+CPL A
+.Ed
 .Sh LEGEND
 List of abbreviations used in this document.
 .Bl -tag -width Ds

src/asm/parser.y

@@ -1874,6 +1874,9 @@ z80_cpl:
 	Z80_CPL {
 		sect_ConstByte(0x2F);
 	}
+	| Z80_CPL MODE_A {
+		sect_ConstByte(0x2F);
+	}
 ;
 
 z80_daa:

test/asm/destination-a.asm

@@ -0,0 +1,21 @@
+SECTION "destination optional", ROM0[0]
+
+MACRO both
+	REDEF op EQUS "\1"
+	SHIFT
+	{op} \#
+	if _NARG
+		{op} a, \#
+	else
+		{op} a
+	endc
+ENDM
+
+	both cpl
+	both add, b
+	both adc, 42
+	both sub, 69
+	both sbc, c
+	both and, d
+	both or, %1010
+	both xor, $80

test/asm/destination-a.out.bin

@@ -0,0 +1,3 @@
+//<2F><><EFBFBD>*<2A>*<2A>E<EFBFBD>E<EFBFBD><45><EFBFBD><EFBFBD><EFBFBD>
+<EFBFBD>
+<EFBFBD><EFBFBD><EFBFBD><EFBFBD>