From 47442941b6a9480b14d784336fbb79c80b3000d8 Mon Sep 17 00:00:00 2001
From: Rangi <35663410+Rangi42@users.noreply.github.com>
Date: Mon, 1 Nov 2021 19:16:52 -0400
Subject: [PATCH] Support ! operator for condition codes (#720)

Fixes #719
---
 src/asm/parser.y       |  15 +++++++++++----
 src/gbz80.7            |   2 ++
 test/asm/ccode.asm     |  21 +++++++++++++++++++++
 test/asm/ccode.err     |   0
 test/asm/ccode.out     |   0
 test/asm/ccode.out.bin | Bin 0 -> 33 bytes
 6 files changed, 34 insertions(+), 4 deletions(-)
 create mode 100644 test/asm/ccode.asm
 create mode 100644 test/asm/ccode.err
 create mode 100644 test/asm/ccode.out
 create mode 100644 test/asm/ccode.out.bin

diff --git a/src/asm/parser.y b/src/asm/parser.y
index fe69ab4b..b1eb329a 100644
--- a/src/asm/parser.y
+++ b/src/asm/parser.y
@@ -653,6 +653,7 @@ enum {
 %type	<constValue>	reg_ss
 %type	<constValue>	reg_rr
 %type	<constValue>	reg_tt
+%type	<constValue>	ccode_expr
 %type	<constValue>	ccode
 %type	<expr>		op_a_n
 %type	<constValue>	op_a_r
@@ -1775,7 +1776,7 @@ z80_call	: T_Z80_CALL reloc_16bit {
 			sect_AbsByte(0xCD);
 			sect_RelWord(&$2, 1);
 		}
-		| T_Z80_CALL ccode T_COMMA reloc_16bit {
+		| T_Z80_CALL ccode_expr T_COMMA reloc_16bit {
 			sect_AbsByte(0xC4 | ($2 << 3));
 			sect_RelWord(&$4, 1);
 		}
@@ -1822,7 +1823,7 @@ z80_jp		: T_Z80_JP reloc_16bit {
 			sect_AbsByte(0xC3);
 			sect_RelWord(&$2, 1);
 		}
-		| T_Z80_JP ccode T_COMMA reloc_16bit {
+		| T_Z80_JP ccode_expr T_COMMA reloc_16bit {
 			sect_AbsByte(0xC2 | ($2 << 3));
 			sect_RelWord(&$4, 1);
 		}
@@ -1835,7 +1836,7 @@ z80_jr		: T_Z80_JR reloc_16bit {
 			sect_AbsByte(0x18);
 			sect_PCRelByte(&$2, 1);
 		}
-		| T_Z80_JR ccode T_COMMA reloc_16bit {
+		| T_Z80_JR ccode_expr T_COMMA reloc_16bit {
 			sect_AbsByte(0x20 | ($2 << 3));
 			sect_PCRelByte(&$4, 1);
 		}
@@ -2017,7 +2018,7 @@ z80_res		: T_Z80_RES const_3bit T_COMMA reg_r {
 ;
 
 z80_ret		: T_Z80_RET { sect_AbsByte(0xC9); }
-		| T_Z80_RET ccode { sect_AbsByte(0xC0 | ($2 << 3)); }
+		| T_Z80_RET ccode_expr { sect_AbsByte(0xC0 | ($2 << 3)); }
 ;
 
 z80_reti	: T_Z80_RETI { sect_AbsByte(0xD9); }
@@ -2172,6 +2173,12 @@ T_MODE_L	: T_TOKEN_L
 		| T_OP_LOW T_LPAREN T_MODE_HL T_RPAREN
 ;
 
+ccode_expr	: ccode
+		| T_OP_LOGICNOT ccode_expr {
+			$$ = $2 ^ 1;
+		}
+;
+
 ccode		: T_CC_NZ { $$ = CC_NZ; }
 		| T_CC_Z { $$ = CC_Z; }
 		| T_CC_NC { $$ = CC_NC; }
diff --git a/src/gbz80.7 b/src/gbz80.7
index 490bc01d..7d79de78 100644
--- a/src/gbz80.7
+++ b/src/gbz80.7
@@ -62,6 +62,8 @@ Execute if Z is not set.
 Execute if C is set.
 .It Sy NC
 Execute if C is not set.
+.It Sy ! cc
+Negates a condition code.
 .El
 .It Ar vec
 One of the
diff --git a/test/asm/ccode.asm b/test/asm/ccode.asm
new file mode 100644
index 00000000..6a132214
--- /dev/null
+++ b/test/asm/ccode.asm
@@ -0,0 +1,21 @@
+SECTION "ccode test", ROM0[0]
+
+Label:
+
+.local1
+	jp z, Label
+	jr nz, .local1
+	call c, Label
+	call nc, Label
+
+.local2
+	jp !nz, Label
+	jr !z, .local2
+	call !nc, Label
+	call !c, Label
+
+.local3
+	jp !!z, Label
+	jr !!nz, .local3
+	call !!c, Label
+	call !!nc, Label
diff --git a/test/asm/ccode.err b/test/asm/ccode.err
new file mode 100644
index 00000000..e69de29b
diff --git a/test/asm/ccode.out b/test/asm/ccode.out
new file mode 100644
index 00000000..e69de29b
diff --git a/test/asm/ccode.out.bin b/test/asm/ccode.out.bin
new file mode 100644
index 0000000000000000000000000000000000000000..ffc78aa873f828026fa97c487eef8ac68f53fa0c
GIT binary patch
literal 33
VcmX@bz@YH^4g<p#28L5unE<}y3cvsW

literal 0
HcmV?d00001