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https://github.com/gbdev/rgbds.git
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6e123ccc36
Instead of allocating 0x4000 bytes for all sections and resize them as needed, allocate 0x8000 bytes and don't let them to be resized. This is the max possible size (ROM0 when ROMX sections aren't present). Buffers are not needed for RAM sections, this patch changes the code so that it only allocates buffers for ROM sections. Signed-off-by: Antonio Niño Díaz <antonio_nd@outlook.com>
133 lines
2.2 KiB
C
133 lines
2.2 KiB
C
/* GB Z80 instruction groups
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n3 = 3-bit
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n = 8-bit
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nn = 16-bit
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* ADC A,n : 0xCE
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* ADC A,r : 0x88|r
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* ADD A,n : 0xC6
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* ADD A,r : 0x80|r
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* ADD HL,ss : 0x09|(ss<<4)
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* ADD SP,n : 0xE8
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* AND A,n : 0xE6
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* AND A,r : 0xA0|r
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* BIT n3,r : 0xCB 0x40|(n3<<3)|r
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* CALL cc,nn : 0xC4|(cc<<3)
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* CALL nn : 0xCD
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* CCF : 0x3F
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* CP A,n : 0xFE
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* CP A,r : 0xB8|r
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* CPL : 0x2F
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* DAA : 0x27
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* DEC r : 0x05|(r<<3)
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* DEC ss : 0x0B|(ss<<4)
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* DI : 0xF3
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* EI : 0xFB
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* HALT : 0x76
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* INC r : 0x04|(r<<3)
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* INC ss : 0x03|(ss<<4)
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* JP HL : 0xE9
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* JP cc,nn : 0xC2|(cc<<3)
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* JP nn : 0xC3|(cc<<3)
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* JR n : 0x18
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* JR cc,n : 0x20|(cc<<3)
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* LD (nn),SP : 0x08
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* LD ($FF00+C),A : 0xE2
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* LD ($FF00+n),A : 0xE0
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* LD (nn),A : 0xEA
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* LD (rr),A : 0x02|(rr<<4) // HL+ and HL- included
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* LD A,($FF00+C) : 0xF2
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* LD A,($FF00+n) : 0xF0
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* LD A,(nn) : 0xFA
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* LD A,(rr) : 0x0A|(rr<<4) // HL+ and HL- included
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* LD HL,SP+n : 0xF8
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* LD SP,HL : 0xF9
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* LD r,n : 0x06|(r<<3)
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* LD r,r' : 0x40|(r<<3)|r' // NOTE: LD (HL),(HL) not allowed
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* LD ss,nn : 0x01|(ss<<4)
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* NOP : 0x00
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* OR A,n : 0xF6
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* OR A,r : 0xB0|r
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* POP tt : 0xC1|(tt<<4)
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* PUSH tt : 0xC5|(tt<<4)
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* RES n3,r : 0xCB 0x80|(n3<<3)|r
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* RET : 0xC9
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* RET cc : 0xC0|(cc<<3)
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* RETI : 0xD9
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* RL r : 0xCB 0x10|r
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* RLA : 0x17
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* RLC r : 0xCB 0x00|r
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* RLCA : 0x07
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* RR r : 0xCB 0x18|r
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* RRA : 0x1F
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* RRC r : 0xCB 0x08|r
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* RRCA : 0x0F
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* RST n : 0xC7|n
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* SBC A,n : 0xDE
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* SBC A,r : 0x98|r
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* SCF : 0x37
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* SET n3,r : 0xCB 0xC0|(n8<<3)|r
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* SLA r : 0xCB 0x20|r
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* SRA r : 0xCB 0x28|r
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* SRL r : 0xCB 0x38|r
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* STOP : 0x10 0x00
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* SUB A,n : 0xD6
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* SUB A,r : 0x90|r
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* SWAP r : 0xCB 0x30|r
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* XOR A,n : 0xEE
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* XOR A,r : 0xA8|r
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*/
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#define NAME_DB "db"
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#define NAME_DW "dw"
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#define NAME_RB "rb"
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#define NAME_RW "rw"
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/* "r" defs */
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enum {
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REG_B = 0,
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REG_C,
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REG_D,
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REG_E,
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REG_H,
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REG_L,
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REG_HL_IND,
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REG_A
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};
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/* "rr" defs */
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enum {
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REG_BC_IND = 0,
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REG_DE_IND,
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REG_HL_INDINC,
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REG_HL_INDDEC,
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};
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/* "ss" defs */
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enum {
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REG_BC = 0,
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REG_DE,
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REG_HL,
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REG_SP
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};
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/* "tt" defs */
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/*
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#define REG_BC 0
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#define REG_DE 1
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#define REG_HL 2
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*/
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#define REG_AF 3
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/* "cc" defs */
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enum {
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CC_NZ = 0,
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CC_Z,
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CC_NC,
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CC_C
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};
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