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As reported by the following command: mandoc -T lint man/* | grep -v "input text line longer than 80 bytes" (One of them also showed up as a warning while setting up Debian packaging.)
1957 lines
28 KiB
Groff
1957 lines
28 KiB
Groff
.\" SPDX-License-Identifier: MIT
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.\"
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.Dd March 28, 2021
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.Dt GBZ80 7
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.Os
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.Sh NAME
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.Nm gbz80
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.Nd CPU opcode reference
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.Sh DESCRIPTION
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This is the list of opcodes supported by
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.Xr rgbasm 1 ,
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including a short description, the number of bytes needed to encode them and the number of CPU cycles at 1MHz (or 2MHz in GBC dual speed mode) needed to complete them.
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.Pp
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Note: All arithmetic/logic operations that use register
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.Sy A
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as destination can omit the destination as it is assumed to be register
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.Sy A
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by default.
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The following two lines have the same effect:
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.Bd -literal -offset indent
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OR A,B
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OR B
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.Ed
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.Sh LEGEND
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List of abbreviations used in this document.
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.Bl -tag -width Ds
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.It Ar r8
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Any of the 8-bit registers
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.Pq Sy A , B , C , D , E , H , L .
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.It Ar r16
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Any of the general-purpose 16-bit registers
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.Pq Sy BC , DE , HL .
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.It Ar n8
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8-bit integer constant.
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.It Ar n16
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16-bit integer constant.
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.It Ar e8
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8-bit offset
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.Po Sy -128
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to
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.Sy 127
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.Pc .
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.It Ar u3
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3-bit unsigned integer constant
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.Po Sy 0
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to
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.Sy 7
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.Pc .
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.It Ar cc
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Condition codes:
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.Bl -tag -width Ds -compact
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.It Sy Z
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Execute if Z is set.
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.It Sy NZ
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Execute if Z is not set.
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.It Sy C
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Execute if C is set.
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.It Sy NC
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Execute if C is not set.
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.It Sy ! cc
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Negates a condition code.
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.El
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.It Ar vec
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One of the
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.Sy RST
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vectors
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.Po Ad 0x00 , 0x08 , 0x10 , 0x18 , 0x20 , 0x28 , 0x30 ,
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and
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.Ad 0x38 Pc .
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.El
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.Sh INSTRUCTION OVERVIEW
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.Ss 8-bit Arithmetic and Logic Instructions
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.Bl -inset -compact
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.It Sx ADC A,r8
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.It Sx ADC A,[HL]
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.It Sx ADC A,n8
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.It Sx ADD A,r8
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.It Sx ADD A,[HL]
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.It Sx ADD A,n8
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.It Sx AND A,r8
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.It Sx AND A,[HL]
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.It Sx AND A,n8
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.It Sx CP A,r8
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.It Sx CP A,[HL]
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.It Sx CP A,n8
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.It Sx DEC r8
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.It Sx DEC [HL]
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.It Sx INC r8
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.It Sx INC [HL]
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.It Sx OR A,r8
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.It Sx OR A,[HL]
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.It Sx OR A,n8
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.It Sx SBC A,r8
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.It Sx SBC A,[HL]
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.It Sx SBC A,n8
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.It Sx SUB A,r8
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.It Sx SUB A,[HL]
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.It Sx SUB A,n8
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.It Sx XOR A,r8
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.It Sx XOR A,[HL]
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.It Sx XOR A,n8
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.El
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.Ss 16-bit Arithmetic Instructions
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.Bl -inset -compact
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.It Sx ADD HL,r16
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.It Sx DEC r16
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.It Sx INC r16
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.El
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.Ss Bit Operations Instructions
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.Bl -inset -compact
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.It Sx BIT u3,r8
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.It Sx BIT u3,[HL]
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.It Sx RES u3,r8
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.It Sx RES u3,[HL]
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.It Sx SET u3,r8
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.It Sx SET u3,[HL]
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.It Sx SWAP r8
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.It Sx SWAP [HL]
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.El
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.Ss Bit Shift Instructions
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.Bl -inset -compact
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.It Sx RL r8
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.It Sx RL [HL]
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.It Sx RLA
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.It Sx RLC r8
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.It Sx RLC [HL]
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.It Sx RLCA
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.It Sx RR r8
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.It Sx RR [HL]
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.It Sx RRA
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.It Sx RRC r8
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.It Sx RRC [HL]
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.It Sx RRCA
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.It Sx SLA r8
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.It Sx SLA [HL]
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.It Sx SRA r8
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.It Sx SRA [HL]
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.It Sx SRL r8
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.It Sx SRL [HL]
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.El
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.Ss Load Instructions
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.Bl -inset -compact
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.It Sx LD r8,r8
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.It Sx LD r8,n8
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.It Sx LD r16,n16
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.It Sx LD [HL],r8
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.It Sx LD [HL],n8
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.It Sx LD r8,[HL]
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.It Sx LD [r16],A
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.It Sx LD [n16],A
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.It Sx LDH [n16],A
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.It Sx LDH [C],A
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.It Sx LD A,[r16]
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.It Sx LD A,[n16]
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.It Sx LDH A,[n16]
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.It Sx LDH A,[C]
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.It Sx LD [HLI],A
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.It Sx LD [HLD],A
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.It Sx LD A,[HLI]
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.It Sx LD A,[HLD]
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.El
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.Ss Jumps and Subroutines
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.Bl -inset -compact
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.It Sx CALL n16
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.It Sx CALL cc,n16
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.It Sx JP HL
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.It Sx JP n16
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.It Sx JP cc,n16
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.It Sx JR n16
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.It Sx JR cc,n16
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.It Sx RET cc
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.It Sx RET
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.It Sx RETI
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.It Sx RST vec
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.El
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.Ss Stack Operations Instructions
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.Bl -inset -compact
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.It Sx ADD HL,SP
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.It Sx ADD SP,e8
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.It Sx DEC SP
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.It Sx INC SP
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.It Sx LD SP,n16
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.It Sx LD [n16],SP
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.It Sx LD HL,SP+e8
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.It Sx LD SP,HL
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.It Sx POP AF
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.It Sx POP r16
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.It Sx PUSH AF
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.It Sx PUSH r16
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.El
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.Ss Miscellaneous Instructions
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.Bl -inset -compact
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.It Sx CCF
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.It Sx CPL
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.It Sx DAA
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.It Sx DI
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.It Sx EI
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.It Sx HALT
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.It Sx NOP
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.It Sx SCF
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.It Sx STOP
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.El
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.Sh INSTRUCTION REFERENCE
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.Ss ADC A,r8
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Add the value in
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.Ar r8
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plus the carry flag to
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.Sy A .
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.Pp
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Cycles: 1
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.Pp
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Bytes: 1
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.Pp
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Flags:
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.Bl -hang -compact
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.It Sy Z
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Set if result is 0.
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.It Sy N
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0
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.It Sy H
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Set if overflow from bit 3.
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.It Sy C
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Set if overflow from bit 7.
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.El
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.Ss ADC A,[HL]
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Add the byte pointed to by
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.Sy HL
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plus the carry flag to
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.Sy A .
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.Pp
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Cycles: 2
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.Pp
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Bytes: 1
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.Pp
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Flags: See
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.Sx ADC A,r8
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.Ss ADC A,n8
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Add the value
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.Ar n8
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plus the carry flag to
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.Sy A .
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.Pp
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Cycles: 2
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.Pp
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Bytes: 2
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.Pp
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Flags: See
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.Sx ADC A,r8
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.Ss ADD A,r8
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Add the value in
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.Ar r8
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to
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.Sy A .
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.Pp
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Cycles: 1
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.Pp
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Bytes: 1
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.Pp
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Flags:
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.Bl -hang -compact
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.It Sy Z
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Set if result is 0.
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.It Sy N
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0
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.It Sy H
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Set if overflow from bit 3.
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.It Sy C
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Set if overflow from bit 7.
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.El
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.Ss ADD A,[HL]
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Add the byte pointed to by
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.Sy HL
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to
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.Sy A .
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.Pp
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Cycles: 2
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.Pp
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Bytes: 1
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.Pp
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Flags: See
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.Sx ADD A,r8
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.Ss ADD A,n8
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Add the value
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.Ar n8
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to
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.Sy A .
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.Pp
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Cycles: 2
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.Pp
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Bytes: 2
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.Pp
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Flags: See
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.Sx ADD A,r8
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.Ss ADD HL,r16
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Add the value in
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.Ar r16
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to
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.Sy HL .
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.Pp
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Cycles: 2
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.Pp
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Bytes: 1
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.Pp
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Flags:
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.Bl -hang -compact
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.It Sy N
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0
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.It Sy H
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Set if overflow from bit 11.
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.It Sy C
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Set if overflow from bit 15.
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.El
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.Ss ADD HL,SP
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Add the value in
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.Sy SP
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to
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.Sy HL .
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.Pp
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Cycles: 2
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.Pp
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Bytes: 1
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.Pp
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Flags: See
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.Sx ADD HL,r16
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.Ss ADD SP,e8
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Add the signed value
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.Ar e8
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to
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.Sy SP .
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.Pp
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Cycles: 4
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.Pp
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Bytes: 2
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.Pp
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Flags:
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.Bl -hang -compact
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.It Sy Z
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0
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.It Sy N
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0
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.It Sy H
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Set if overflow from bit 3.
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.It Sy C
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Set if overflow from bit 7.
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.El
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.Ss AND A,r8
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Bitwise AND between the value in
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.Ar r8
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and
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.Sy A .
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.Pp
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Cycles: 1
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.Pp
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Bytes: 1
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.Pp
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Flags:
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.Bl -hang -compact
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.It Sy Z
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Set if result is 0.
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.It Sy N
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0
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.It Sy H
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1
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.It Sy C
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0
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.El
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.Ss AND A,[HL]
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Bitwise AND between the byte pointed to by
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.Sy HL
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and
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.Sy A .
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.Pp
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Cycles: 2
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.Pp
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Bytes: 1
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.Pp
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Flags: See
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.Sx AND A,r8
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.Ss AND A,n8
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Bitwise AND between the value in
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.Ar n8
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and
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.Sy A .
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.Pp
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Cycles: 2
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.Pp
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Bytes: 2
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.Pp
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Flags: See
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.Sx AND A,r8
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.Ss BIT u3,r8
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Test bit
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.Ar u3
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in register
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.Ar r8 ,
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set the zero flag if bit not set.
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.Pp
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Cycles: 2
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.Pp
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Bytes: 2
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.Pp
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Flags:
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.Bl -hang -compact
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.It Sy Z
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Set if the selected bit is 0.
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.It Sy N
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0
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.It Sy H
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1
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.El
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.Ss BIT u3,[HL]
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Test bit
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.Ar u3
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in the byte pointed by
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.Sy HL ,
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set the zero flag if bit not set.
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.Pp
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Cycles: 3
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.Pp
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Bytes: 2
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.Pp
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Flags: See
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.Sx BIT u3,r8
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.Ss CALL n16
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Call address
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.Ar n16 .
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This pushes the address of the instruction after the
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.Sy CALL
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on the stack, such that
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.Sx RET
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can pop it later; then, it executes an implicit
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.Sx JP n16 .
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.Pp
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Cycles: 6
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.Pp
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Bytes: 3
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.Pp
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Flags: None affected.
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.Ss CALL cc,n16
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Call address
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.Ar n16
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if condition
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.Ar cc
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is met.
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.Pp
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Cycles: 6 taken / 3 untaken
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.Pp
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Bytes: 3
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.Pp
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Flags: None affected.
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.Ss CCF
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Complement Carry Flag.
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.Pp
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Cycles: 1
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.Pp
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Bytes: 1
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.Pp
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Flags:
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.Bl -hang -compact
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.It Sy N
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0
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.It Sy H
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0
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.It Sy C
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Inverted.
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.El
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.Ss CP A,r8
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Subtract the value in
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.Ar r8
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from
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.Sy A
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and set flags accordingly, but don't store the result.
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This is useful for ComParing values.
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.Pp
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Cycles: 1
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.Pp
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Bytes: 1
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.Pp
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Flags:
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.Bl -hang -compact
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.It Sy Z
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Set if result is 0.
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.It Sy N
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1
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.It Sy H
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Set if borrow from bit 4.
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.It Sy C
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Set if borrow (i.e. if
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.Ar r8
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>
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.Sy A ) .
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.El
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.Ss CP A,[HL]
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Subtract the byte pointed to by
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.Sy HL
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from
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.Sy A
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and set flags accordingly, but don't store the result.
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.Pp
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Cycles: 2
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.Pp
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Bytes: 1
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.Pp
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Flags: See
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.Sx CP A,r8
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.Ss CP A,n8
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Subtract the value
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.Ar n8
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from
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.Sy A
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and set flags accordingly, but don't store the result.
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.Pp
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Cycles: 2
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.Pp
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Bytes: 2
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.Pp
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Flags: See
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.Sx CP A,r8
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.Ss CPL
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ComPLement accumulator
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.Po Sy A
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=
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.Sy ~A
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.Pc .
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.Pp
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Cycles: 1
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.Pp
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Bytes: 1
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.Pp
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Flags:
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.Bl -hang -compact
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.It Sy N
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1
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.It Sy H
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1
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.El
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.Ss DAA
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Decimal Adjust Accumulator to get a correct BCD representation after an arithmetic instruction.
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.Pp
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Cycles: 1
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.Pp
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Bytes: 1
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.Pp
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Flags:
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.Bl -hang -compact
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.It Sy Z
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Set if result is 0.
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.It Sy H
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0
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.It Sy C
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Set or reset depending on the operation.
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.El
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.Ss DEC r8
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Decrement value in register
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.Ar r8
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by 1.
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.Pp
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Cycles: 1
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.Pp
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Bytes: 1
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.Pp
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Flags:
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.Bl -hang -compact
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.It Sy Z
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Set if result is 0.
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.It Sy N
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1
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.It Sy H
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Set if borrow from bit 4.
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.El
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.Ss DEC [HL]
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Decrement the byte pointed to by
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.Sy HL
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by 1.
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.Pp
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Cycles: 3
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.Pp
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Bytes: 1
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.Pp
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Flags: See
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.Sx DEC r8
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.Ss DEC r16
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Decrement value in register
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.Ar r16
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by 1.
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.Pp
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Cycles: 2
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.Pp
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Bytes: 1
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.Pp
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Flags: None affected.
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.Ss DEC SP
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Decrement value in register
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.Sy SP
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by 1.
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.Pp
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Cycles: 2
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.Pp
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Bytes: 1
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.Pp
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Flags: None affected.
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.Ss DI
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Disable Interrupts by clearing the
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.Sy IME
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flag.
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.Pp
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Cycles: 1
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.Pp
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Bytes: 1
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.Pp
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Flags: None affected.
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.Ss EI
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Enable Interrupts by setting the
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.Sy IME
|
|
flag.
|
|
The flag is only set
|
|
.Em after
|
|
the instruction following
|
|
.Sy EI .
|
|
.Pp
|
|
Cycles: 1
|
|
.Pp
|
|
Bytes: 1
|
|
.Pp
|
|
Flags: None affected.
|
|
.Ss HALT
|
|
Enter CPU low-power consumption mode until an interrupt occurs.
|
|
The exact behavior of this instruction depends on the state of the
|
|
.Sy IME
|
|
flag.
|
|
.Bl -tag -width indent
|
|
.It Sy IME No set
|
|
The CPU enters low-power mode until
|
|
.Em after
|
|
an interrupt is about to be serviced.
|
|
The handler is executed normally, and the CPU resumes execution after the
|
|
.Ic HALT
|
|
when that returns.
|
|
.It Sy IME No not set
|
|
The behavior depends on whether an interrupt is pending (i.e.\&
|
|
.Ql [IE] & [IF]
|
|
is non-zero).
|
|
.Bl -tag -width indent
|
|
.It None pending
|
|
As soon as an interrupt becomes pending, the CPU resumes execution.
|
|
This is like the above, except that the handler is
|
|
.Em not
|
|
called.
|
|
.It Some pending
|
|
The CPU continues execution after the
|
|
.Ic HALT ,
|
|
but the byte after it is read twice in a row
|
|
.Po
|
|
.Sy PC
|
|
is not incremented, due to a hardware bug
|
|
.Pc .
|
|
.El
|
|
.El
|
|
.Pp
|
|
Cycles: -
|
|
.Pp
|
|
Bytes: 1
|
|
.Pp
|
|
Flags: None affected.
|
|
.Ss INC r8
|
|
Increment value in register
|
|
.Ar r8
|
|
by 1.
|
|
.Pp
|
|
Cycles: 1
|
|
.Pp
|
|
Bytes: 1
|
|
.Pp
|
|
Flags:
|
|
.Bl -hang -compact
|
|
.It Sy Z
|
|
Set if result is 0.
|
|
.It Sy N
|
|
0
|
|
.It Sy H
|
|
Set if overflow from bit 3.
|
|
.El
|
|
.Ss INC [HL]
|
|
Increment the byte pointed to by
|
|
.Sy HL
|
|
by 1.
|
|
.Pp
|
|
Cycles: 3
|
|
.Pp
|
|
Bytes: 1
|
|
.Pp
|
|
Flags: See
|
|
.Sx INC r8
|
|
.Ss INC r16
|
|
Increment value in register
|
|
.Ar r16
|
|
by 1.
|
|
.Pp
|
|
Cycles: 2
|
|
.Pp
|
|
Bytes: 1
|
|
.Pp
|
|
Flags: None affected.
|
|
.Ss INC SP
|
|
Increment value in register
|
|
.Sy SP
|
|
by 1.
|
|
.Pp
|
|
Cycles: 2
|
|
.Pp
|
|
Bytes: 1
|
|
.Pp
|
|
Flags: None affected.
|
|
.Ss JP n16
|
|
Jump to address
|
|
.Ar n16 ;
|
|
effectively, store
|
|
.Ar n16
|
|
into
|
|
.Sy PC .
|
|
.Pp
|
|
Cycles: 4
|
|
.Pp
|
|
Bytes: 3
|
|
.Pp
|
|
Flags: None affected.
|
|
.Ss JP cc,n16
|
|
Jump to address
|
|
.Ar n16
|
|
if condition
|
|
.Ar cc
|
|
is met.
|
|
.Pp
|
|
Cycles: 4 taken / 3 untaken
|
|
.Pp
|
|
Bytes: 3
|
|
.Pp
|
|
Flags: None affected.
|
|
.Ss JP HL
|
|
Jump to address in
|
|
.Sy HL ;
|
|
effectively, load
|
|
.Sy PC
|
|
with value in register
|
|
.Sy HL .
|
|
.Pp
|
|
Cycles: 1
|
|
.Pp
|
|
Bytes: 1
|
|
.Pp
|
|
Flags: None affected.
|
|
.Ss JR n16
|
|
Relative Jump to address
|
|
.Ar n16 .
|
|
The address is encoded as a signed 8-bit offset from the address immediately following the
|
|
.Ic JR
|
|
instruction, so the target address
|
|
.Ar n16
|
|
must be between
|
|
.Sy -128
|
|
and
|
|
.Sy 127
|
|
bytes away.
|
|
For example:
|
|
.Bd -literal -offset indent
|
|
JR Label ; no-op; encoded offset of 0
|
|
Label:
|
|
JR Label ; infinite loop; encoded offset of -2
|
|
.Ed
|
|
.Pp
|
|
Cycles: 3
|
|
.Pp
|
|
Bytes: 2
|
|
.Pp
|
|
Flags: None affected.
|
|
.Ss JR cc,n16
|
|
Relative Jump to address
|
|
.Ar n16
|
|
if condition
|
|
.Ar cc
|
|
is met.
|
|
.Pp
|
|
Cycles: 3 taken / 2 untaken
|
|
.Pp
|
|
Bytes: 2
|
|
.Pp
|
|
Flags: None affected.
|
|
.Ss LD r8,r8
|
|
Load (copy) value in register on the right into register on the left.
|
|
.Pp
|
|
Cycles: 1
|
|
.Pp
|
|
Bytes: 1
|
|
.Pp
|
|
Flags: None affected.
|
|
.Ss LD r8,n8
|
|
Load value
|
|
.Ar n8
|
|
into register
|
|
.Ar r8 .
|
|
.Pp
|
|
Cycles: 2
|
|
.Pp
|
|
Bytes: 2
|
|
.Pp
|
|
Flags: None affected.
|
|
.Ss LD r16,n16
|
|
Load value
|
|
.Ar n16
|
|
into register
|
|
.Ar r16 .
|
|
.Pp
|
|
Cycles: 3
|
|
.Pp
|
|
Bytes: 3
|
|
.Pp
|
|
Flags: None affected.
|
|
.Ss LD [HL],r8
|
|
Store value in register
|
|
.Ar r8
|
|
into the byte pointed to by register
|
|
.Sy HL .
|
|
.Pp
|
|
Cycles: 2
|
|
.Pp
|
|
Bytes: 1
|
|
.Pp
|
|
Flags: None affected.
|
|
.Ss LD [HL],n8
|
|
Store value
|
|
.Ar n8
|
|
into the byte pointed to by register
|
|
.Sy HL .
|
|
.Pp
|
|
Cycles: 3
|
|
.Pp
|
|
Bytes: 2
|
|
.Pp
|
|
Flags: None affected.
|
|
.Ss LD r8,[HL]
|
|
Load value into register
|
|
.Ar r8
|
|
from the byte pointed to by register
|
|
.Sy HL .
|
|
.Pp
|
|
Cycles: 2
|
|
.Pp
|
|
Bytes: 1
|
|
.Pp
|
|
Flags: None affected.
|
|
.Ss LD [r16],A
|
|
Store value in register
|
|
.Sy A
|
|
into the byte pointed to by register
|
|
.Ar r16 .
|
|
.Pp
|
|
Cycles: 2
|
|
.Pp
|
|
Bytes: 1
|
|
.Pp
|
|
Flags: None affected.
|
|
.Ss LD [n16],A
|
|
Store value in register
|
|
.Sy A
|
|
into the byte at address
|
|
.Ar n16 .
|
|
.Pp
|
|
Cycles: 4
|
|
.Pp
|
|
Bytes: 3
|
|
.Pp
|
|
Flags: None affected.
|
|
.Ss LDH [n16],A
|
|
Store value in register
|
|
.Sy A
|
|
into the byte at address
|
|
.Ar n16 ,
|
|
provided the address is between
|
|
.Ad $FF00
|
|
and
|
|
.Ad $FFFF .
|
|
.Pp
|
|
Cycles: 3
|
|
.Pp
|
|
Bytes: 2
|
|
.Pp
|
|
Flags: None affected.
|
|
.Pp
|
|
This is sometimes written as
|
|
.Ql LDIO [n16],A ,
|
|
or
|
|
.Ql LD [$FF00+n8],A .
|
|
.Ss LDH [C],A
|
|
Store value in register
|
|
.Sy A
|
|
into the byte at address
|
|
.Ad $FF00+C .
|
|
.Pp
|
|
Cycles: 2
|
|
.Pp
|
|
Bytes: 1
|
|
.Pp
|
|
Flags: None affected.
|
|
.Pp
|
|
This is sometimes written as
|
|
.Ql LDIO [C],A ,
|
|
or
|
|
.Ql LD [$FF00+C],A .
|
|
.Ss LD A,[r16]
|
|
Load value in register
|
|
.Sy A
|
|
from the byte pointed to by register
|
|
.Ar r16 .
|
|
.Pp
|
|
Cycles: 2
|
|
.Pp
|
|
Bytes: 1
|
|
.Pp
|
|
Flags: None affected.
|
|
.Ss LD A,[n16]
|
|
Load value in register
|
|
.Sy A
|
|
from the byte at address
|
|
.Ar n16 .
|
|
.Pp
|
|
Cycles: 4
|
|
.Pp
|
|
Bytes: 3
|
|
.Pp
|
|
Flags: None affected.
|
|
.Ss LDH A,[n16]
|
|
Load value in register
|
|
.Sy A
|
|
from the byte at address
|
|
.Ar n16 ,
|
|
provided the address is between
|
|
.Ad $FF00
|
|
and
|
|
.Ad $FFFF .
|
|
.Pp
|
|
Cycles: 3
|
|
.Pp
|
|
Bytes: 2
|
|
.Pp
|
|
Flags: None affected.
|
|
.Pp
|
|
This is sometimes written as
|
|
.Ql LDIO A,[n16] ,
|
|
or
|
|
.Ql LD A,[$FF00+n8] .
|
|
.Ss LDH A,[C]
|
|
Load value in register
|
|
.Sy A
|
|
from the byte at address
|
|
.Ad $FF00+c .
|
|
.Pp
|
|
Cycles: 2
|
|
.Pp
|
|
Bytes: 1
|
|
.Pp
|
|
Flags: None affected.
|
|
.Pp
|
|
This is sometimes written as
|
|
.Ql LDIO A,[C] ,
|
|
or
|
|
.Ql LD A,[$FF00+C] .
|
|
.Ss LD [HLI],A
|
|
Store value in register
|
|
.Sy A
|
|
into the byte pointed by
|
|
.Sy HL
|
|
and increment
|
|
.Sy HL
|
|
afterwards.
|
|
.Pp
|
|
Cycles: 2
|
|
.Pp
|
|
Bytes: 1
|
|
.Pp
|
|
Flags: None affected.
|
|
.Pp
|
|
This is sometimes written as
|
|
.Ql LD [HL+],A ,
|
|
or
|
|
.Ql LDI [HL],A .
|
|
.Ss LD [HLD],A
|
|
Store value in register
|
|
.Sy A
|
|
into the byte pointed by
|
|
.Sy HL
|
|
and decrement
|
|
.Sy HL
|
|
afterwards.
|
|
.Pp
|
|
Cycles: 2
|
|
.Pp
|
|
Bytes: 1
|
|
.Pp
|
|
Flags: None affected.
|
|
.Pp
|
|
This is sometimes written as
|
|
.Ql LD [HL-],A ,
|
|
or
|
|
.Ql LDD [HL],A .
|
|
.Ss LD A,[HLD]
|
|
Load value into register
|
|
.Sy A
|
|
from the byte pointed by
|
|
.Sy HL
|
|
and decrement
|
|
.Sy HL
|
|
afterwards.
|
|
.Pp
|
|
Cycles: 2
|
|
.Pp
|
|
Bytes: 1
|
|
.Pp
|
|
Flags: None affected.
|
|
.Pp
|
|
This is sometimes written as
|
|
.Ql LD A,[HL-] ,
|
|
or
|
|
.Ql LDD A,[HL] .
|
|
.Ss LD A,[HLI]
|
|
Load value into register
|
|
.Sy A
|
|
from the byte pointed by
|
|
.Sy HL
|
|
and increment
|
|
.Sy HL
|
|
afterwards.
|
|
.Pp
|
|
Cycles: 2
|
|
.Pp
|
|
Bytes: 1
|
|
.Pp
|
|
Flags: None affected.
|
|
.Pp
|
|
This is sometimes written as
|
|
.Ql LD A,[HL+] ,
|
|
or
|
|
.Ql LDI A,[HL] .
|
|
.Ss LD SP,n16
|
|
Load value
|
|
.Ar n16
|
|
into register
|
|
.Sy SP .
|
|
.Pp
|
|
Cycles: 3
|
|
.Pp
|
|
Bytes: 3
|
|
.Pp
|
|
Flags: None affected.
|
|
.Ss LD [n16],SP
|
|
Store
|
|
.Sy SP & $FF
|
|
at address
|
|
.Ar n16
|
|
and
|
|
.Sy SP >> 8
|
|
at address
|
|
.Ar n16
|
|
+ 1.
|
|
.Pp
|
|
Cycles: 5
|
|
.Pp
|
|
Bytes: 3
|
|
.Pp
|
|
Flags: None affected.
|
|
.Ss LD HL,SP+e8
|
|
Add the signed value
|
|
.Ar e8
|
|
to
|
|
.Sy SP
|
|
and store the result in
|
|
.Sy HL .
|
|
.Pp
|
|
Cycles: 3
|
|
.Pp
|
|
Bytes: 2
|
|
.Pp
|
|
Flags:
|
|
.Bl -hang -compact
|
|
.It Sy Z
|
|
0
|
|
.It Sy N
|
|
0
|
|
.It Sy H
|
|
Set if overflow from bit 3.
|
|
.It Sy C
|
|
Set if overflow from bit 7.
|
|
.El
|
|
.Ss LD SP,HL
|
|
Load register
|
|
.Sy HL
|
|
into register
|
|
.Sy SP .
|
|
.Pp
|
|
Cycles: 2
|
|
.Pp
|
|
Bytes: 1
|
|
.Pp
|
|
Flags: None affected.
|
|
.Ss NOP
|
|
No OPeration.
|
|
.Pp
|
|
Cycles: 1
|
|
.Pp
|
|
Bytes: 1
|
|
.Pp
|
|
Flags: None affected.
|
|
.Ss OR A,r8
|
|
Store into
|
|
.Sy A
|
|
the bitwise OR of the value in
|
|
.Ar r8
|
|
and
|
|
.Sy A .
|
|
.Pp
|
|
Cycles: 1
|
|
.Pp
|
|
Bytes: 1
|
|
.Pp
|
|
Flags:
|
|
.Bl -hang -compact
|
|
.It Sy Z
|
|
Set if result is 0.
|
|
.It Sy N
|
|
0
|
|
.It Sy H
|
|
0
|
|
.It Sy C
|
|
0
|
|
.El
|
|
.Ss OR A,[HL]
|
|
Store into
|
|
.Sy A
|
|
the bitwise OR of the byte pointed to by
|
|
.Sy HL
|
|
and
|
|
.Sy A .
|
|
.Pp
|
|
Cycles: 2
|
|
.Pp
|
|
Bytes: 1
|
|
.Pp
|
|
Flags: See
|
|
.Sx OR A,r8
|
|
.Ss OR A,n8
|
|
Store into
|
|
.Sy A
|
|
the bitwise OR of
|
|
.Ar n8
|
|
and
|
|
.Sy A .
|
|
.Pp
|
|
Cycles: 2
|
|
.Pp
|
|
Bytes: 2
|
|
.Pp
|
|
Flags: See
|
|
.Sx OR A,r8
|
|
.Ss POP AF
|
|
Pop register
|
|
.Sy AF
|
|
from the stack.
|
|
This is roughly equivalent to the following
|
|
.Em imaginary
|
|
instructions:
|
|
.Bd -literal -offset indent
|
|
ld f, [sp] ; See below for individual flags
|
|
inc sp
|
|
ld a, [sp]
|
|
inc sp
|
|
.Ed
|
|
.Pp
|
|
Cycles: 3
|
|
.Pp
|
|
Bytes: 1
|
|
.Pp
|
|
Flags:
|
|
.Bl -hang -compact
|
|
.It Sy Z
|
|
Set from bit 7 of the popped low byte.
|
|
.It Sy N
|
|
Set from bit 6 of the popped low byte.
|
|
.It Sy H
|
|
Set from bit 5 of the popped low byte.
|
|
.It Sy C
|
|
Set from bit 4 of the popped low byte.
|
|
.El
|
|
.Ss POP r16
|
|
Pop register
|
|
.Ar r16
|
|
from the stack.
|
|
This is roughly equivalent to the following
|
|
.Em imaginary
|
|
instructions:
|
|
.Bd -literal -offset indent
|
|
ld LOW(r16), [sp] ; C, E or L
|
|
inc sp
|
|
ld HIGH(r16), [sp] ; B, D or H
|
|
inc sp
|
|
.Ed
|
|
.Pp
|
|
Cycles: 3
|
|
.Pp
|
|
Bytes: 1
|
|
.Pp
|
|
Flags: None affected.
|
|
.Ss PUSH AF
|
|
Push register
|
|
.Sy AF
|
|
into the stack.
|
|
This is roughly equivalent to the following
|
|
.Em imaginary
|
|
instructions:
|
|
.Bd -literal -offset indent
|
|
dec sp
|
|
ld [sp], a
|
|
dec sp
|
|
ld [sp], flag_Z << 7 | flag_N << 6 | flag_H << 5 | flag_C << 4
|
|
.Ed
|
|
.Pp
|
|
Cycles: 4
|
|
.Pp
|
|
Bytes: 1
|
|
.Pp
|
|
Flags: None affected.
|
|
.Ss PUSH r16
|
|
Push register
|
|
.Ar r16
|
|
into the stack.
|
|
This is roughly equivalent to the following
|
|
.Em imaginary
|
|
instructions:
|
|
.Bd -literal -offset indent
|
|
dec sp
|
|
ld [sp], HIGH(r16) ; B, D or H
|
|
dec sp
|
|
ld [sp], LOW(r16) ; C, E or L
|
|
.Ed
|
|
.Pp
|
|
Cycles: 4
|
|
.Pp
|
|
Bytes: 1
|
|
.Pp
|
|
Flags: None affected.
|
|
.Ss RES u3,r8
|
|
Set bit
|
|
.Ar u3
|
|
in register
|
|
.Ar r8
|
|
to 0.
|
|
Bit 0 is the rightmost one, bit 7 the leftmost one.
|
|
.Pp
|
|
Cycles: 2
|
|
.Pp
|
|
Bytes: 2
|
|
.Pp
|
|
Flags: None affected.
|
|
.Ss RES u3,[HL]
|
|
Set bit
|
|
.Ar u3
|
|
in the byte pointed by
|
|
.Sy HL
|
|
to 0.
|
|
Bit 0 is the rightmost one, bit 7 the leftmost one.
|
|
.Pp
|
|
Cycles: 4
|
|
.Pp
|
|
Bytes: 2
|
|
.Pp
|
|
Flags: None affected.
|
|
.Ss RET
|
|
Return from subroutine.
|
|
This is basically a
|
|
.Sy POP PC
|
|
(if such an instruction existed).
|
|
See
|
|
.Sx POP r16
|
|
for an explanation of how
|
|
.Sy POP
|
|
works.
|
|
.Pp
|
|
Cycles: 4
|
|
.Pp
|
|
Bytes: 1
|
|
.Pp
|
|
Flags: None affected.
|
|
.Ss RET cc
|
|
Return from subroutine if condition
|
|
.Ar cc
|
|
is met.
|
|
.Pp
|
|
Cycles: 5 taken / 2 untaken
|
|
.Pp
|
|
Bytes: 1
|
|
.Pp
|
|
Flags: None affected.
|
|
.Ss RETI
|
|
Return from subroutine and enable interrupts.
|
|
This is basically equivalent to executing
|
|
.Sx EI
|
|
then
|
|
.Sx RET ,
|
|
meaning that
|
|
.Sy IME
|
|
is set right after this instruction.
|
|
.Pp
|
|
Cycles: 4
|
|
.Pp
|
|
Bytes: 1
|
|
.Pp
|
|
Flags: None affected.
|
|
.Ss RL r8
|
|
Rotate bits in register
|
|
.Ar r8
|
|
left, through the carry flag.
|
|
.Bd -literal
|
|
┏━ Flags ━┓ ┏━━━━━━━ r8 ━━━━━━┓
|
|
┌─╂─ C ←╂─╂─ b7 ← ... ← b0 ←╂─┐
|
|
│ ┗━━━━━━━━━┛ ┗━━━━━━━━━━━━━━━━━┛ │
|
|
└─────────────────────────────────┘
|
|
.Ed
|
|
.Pp
|
|
Cycles: 2
|
|
.Pp
|
|
Bytes: 2
|
|
.Pp
|
|
Flags:
|
|
.Bl -hang -compact
|
|
.It Sy Z
|
|
Set if result is 0.
|
|
.It Sy N
|
|
0
|
|
.It Sy H
|
|
0
|
|
.It Sy C
|
|
Set according to result.
|
|
.El
|
|
.Ss RL [HL]
|
|
Rotate the byte pointed to by
|
|
.Sy HL
|
|
left, through the carry flag.
|
|
.Bd -literal
|
|
┏━ Flags ━┓ ┏━━━━━━ [HL] ━━━━━┓
|
|
┌─╂─ C ←╂─╂─ b7 ← ... ← b0 ←╂─┐
|
|
│ ┗━━━━━━━━━┛ ┗━━━━━━━━━━━━━━━━━┛ │
|
|
└─────────────────────────────────┘
|
|
.Ed
|
|
.Pp
|
|
Cycles: 4
|
|
.Pp
|
|
Bytes: 2
|
|
.Pp
|
|
Flags: See
|
|
.Sx RL r8
|
|
.Ss RLA
|
|
Rotate register
|
|
.Sy A
|
|
left, through the carry flag.
|
|
.Bd -literal
|
|
┏━ Flags ━┓ ┏━━━━━━━ A ━━━━━━━┓
|
|
┌─╂─ C ←╂─╂─ b7 ← ... ← b0 ←╂─┐
|
|
│ ┗━━━━━━━━━┛ ┗━━━━━━━━━━━━━━━━━┛ │
|
|
└─────────────────────────────────┘
|
|
.Ed
|
|
.Pp
|
|
Cycles: 1
|
|
.Pp
|
|
Bytes: 1
|
|
.Pp
|
|
Flags:
|
|
.Bl -hang -compact
|
|
.It Sy Z
|
|
0
|
|
.It Sy N
|
|
0
|
|
.It Sy H
|
|
0
|
|
.It Sy C
|
|
Set according to result.
|
|
.El
|
|
.Ss RLC r8
|
|
Rotate register
|
|
.Ar r8
|
|
left.
|
|
.Bd -literal
|
|
┏━ Flags ━┓ ┏━━━━━━━ r8 ━━━━━━┓
|
|
┃ C ←╂─┬─╂─ b7 ← ... ← b0 ←╂─┐
|
|
┗━━━━━━━━━┛ │ ┗━━━━━━━━━━━━━━━━━┛ │
|
|
└─────────────────────┘
|
|
.Ed
|
|
.Pp
|
|
Cycles: 2
|
|
.Pp
|
|
Bytes: 2
|
|
.Pp
|
|
Flags:
|
|
.Bl -hang -compact
|
|
.It Sy Z
|
|
Set if result is 0.
|
|
.It Sy N
|
|
0
|
|
.It Sy H
|
|
0
|
|
.It Sy C
|
|
Set according to result.
|
|
.El
|
|
.Ss RLC [HL]
|
|
Rotate the byte pointed to by
|
|
.Sy HL
|
|
left.
|
|
.Bd -literal
|
|
┏━ Flags ━┓ ┏━━━━━━ [HL] ━━━━━┓
|
|
┃ C ←╂─┬─╂─ b7 ← ... ← b0 ←╂─┐
|
|
┗━━━━━━━━━┛ │ ┗━━━━━━━━━━━━━━━━━┛ │
|
|
└─────────────────────┘
|
|
.Ed
|
|
.Pp
|
|
Cycles: 4
|
|
.Pp
|
|
Bytes: 2
|
|
.Pp
|
|
Flags: See
|
|
.Sx RLC r8
|
|
.Ss RLCA
|
|
Rotate register
|
|
.Sy A
|
|
left.
|
|
.Bd -literal
|
|
┏━ Flags ━┓ ┏━━━━━━━ A ━━━━━━━┓
|
|
┃ C ←╂─┬─╂─ b7 ← ... ← b0 ←╂─┐
|
|
┗━━━━━━━━━┛ │ ┗━━━━━━━━━━━━━━━━━┛ │
|
|
└─────────────────────┘
|
|
.Ed
|
|
.Pp
|
|
Cycles: 1
|
|
.Pp
|
|
Bytes: 1
|
|
.Pp
|
|
Flags:
|
|
.Bl -hang -compact
|
|
.It Sy Z
|
|
0
|
|
.It Sy N
|
|
0
|
|
.It Sy H
|
|
0
|
|
.It Sy C
|
|
Set according to result.
|
|
.El
|
|
.Ss RR r8
|
|
Rotate register
|
|
.Ar r8
|
|
right, through the carry flag.
|
|
.Bd -literal
|
|
┏━━━━━━━ r8 ━━━━━━┓ ┏━ Flags ━┓
|
|
┌─╂→ b7 → ... → b0 ─╂─╂→ C ─╂─┐
|
|
│ ┗━━━━━━━━━━━━━━━━━┛ ┗━━━━━━━━━┛ │
|
|
└─────────────────────────────────┘
|
|
.Ed
|
|
.Pp
|
|
Cycles: 2
|
|
.Pp
|
|
Bytes: 2
|
|
.Pp
|
|
Flags:
|
|
.Bl -hang -compact
|
|
.It Sy Z
|
|
Set if result is 0.
|
|
.It Sy N
|
|
0
|
|
.It Sy H
|
|
0
|
|
.It Sy C
|
|
Set according to result.
|
|
.El
|
|
.Ss RR [HL]
|
|
Rotate the byte pointed to by
|
|
.Sy HL
|
|
right, through the carry flag.
|
|
.Bd -literal
|
|
┏━━━━━━ [HL] ━━━━━┓ ┏━ Flags ━┓
|
|
┌─╂→ b7 → ... → b0 ─╂─╂→ C ─╂─┐
|
|
│ ┗━━━━━━━━━━━━━━━━━┛ ┗━━━━━━━━━┛ │
|
|
└─────────────────────────────────┘
|
|
.Ed
|
|
.Pp
|
|
Cycles: 4
|
|
.Pp
|
|
Bytes: 2
|
|
.Pp
|
|
Flags: See
|
|
.Sx RR r8
|
|
.Ss RRA
|
|
Rotate register
|
|
.Sy A
|
|
right, through the carry flag.
|
|
.Bd -literal
|
|
┏━━━━━━━ A ━━━━━━━┓ ┏━ Flags ━┓
|
|
┌─╂→ b7 → ... → b0 ─╂─╂→ C ─╂─┐
|
|
│ ┗━━━━━━━━━━━━━━━━━┛ ┗━━━━━━━━━┛ │
|
|
└─────────────────────────────────┘
|
|
.Ed
|
|
.Pp
|
|
Cycles: 1
|
|
.Pp
|
|
Bytes: 1
|
|
.Pp
|
|
Flags:
|
|
.Bl -hang -compact
|
|
.It Sy Z
|
|
0
|
|
.It Sy N
|
|
0
|
|
.It Sy H
|
|
0
|
|
.It Sy C
|
|
Set according to result.
|
|
.El
|
|
.Ss RRC r8
|
|
Rotate register
|
|
.Ar r8
|
|
right.
|
|
.Bd -literal
|
|
┏━━━━━━━ r8 ━━━━━━┓ ┏━ Flags ━┓
|
|
┌─╂→ b7 → ... → b0 ─╂─┬─╂→ C ┃
|
|
│ ┗━━━━━━━━━━━━━━━━━┛ │ ┗━━━━━━━━━┛
|
|
└─────────────────────┘
|
|
.Ed
|
|
.Pp
|
|
Cycles: 2
|
|
.Pp
|
|
Bytes: 2
|
|
.Pp
|
|
Flags:
|
|
.Bl -hang -compact
|
|
.It Sy Z
|
|
Set if result is 0.
|
|
.It Sy N
|
|
0
|
|
.It Sy H
|
|
0
|
|
.It Sy C
|
|
Set according to result.
|
|
.El
|
|
.Ss RRC [HL]
|
|
Rotate the byte pointed to by
|
|
.Sy HL
|
|
right.
|
|
.Bd -literal
|
|
┏━━━━━━ [HL] ━━━━━┓ ┏━ Flags ━┓
|
|
┌─╂→ b7 → ... → b0 ─╂─┬─╂→ C ┃
|
|
│ ┗━━━━━━━━━━━━━━━━━┛ │ ┗━━━━━━━━━┛
|
|
└─────────────────────┘
|
|
.Ed
|
|
.Pp
|
|
Cycles: 4
|
|
.Pp
|
|
Bytes: 2
|
|
.Pp
|
|
Flags: See
|
|
.Sx RRC r8
|
|
.Ss RRCA
|
|
Rotate register
|
|
.Sy A
|
|
right.
|
|
.Bd -literal
|
|
┏━━━━━━━ A ━━━━━━━┓ ┏━ Flags ━┓
|
|
┌─╂→ b7 → ... → b0 ─╂─┬─╂→ C ┃
|
|
│ ┗━━━━━━━━━━━━━━━━━┛ │ ┗━━━━━━━━━┛
|
|
└─────────────────────┘
|
|
.Ed
|
|
.Pp
|
|
Cycles: 1
|
|
.Pp
|
|
Bytes: 1
|
|
.Pp
|
|
Flags:
|
|
.Bl -hang -compact
|
|
.It Sy Z
|
|
0
|
|
.It Sy N
|
|
0
|
|
.It Sy H
|
|
0
|
|
.It Sy C
|
|
Set according to result.
|
|
.El
|
|
.Ss RST vec
|
|
Call address
|
|
.Ar vec .
|
|
This is a shorter and faster equivalent to
|
|
.Sx CALL
|
|
for suitable values of
|
|
.Ar vec .
|
|
.Pp
|
|
Cycles: 4
|
|
.Pp
|
|
Bytes: 1
|
|
.Pp
|
|
Flags: None affected.
|
|
.Ss SBC A,r8
|
|
Subtract the value in
|
|
.Ar r8
|
|
and the carry flag from
|
|
.Sy A .
|
|
.Pp
|
|
Cycles: 1
|
|
.Pp
|
|
Bytes: 1
|
|
.Pp
|
|
Flags:
|
|
.Bl -hang -compact
|
|
.It Sy Z
|
|
Set if result is 0.
|
|
.It Sy N
|
|
1
|
|
.It Sy H
|
|
Set if borrow from bit 4.
|
|
.It Sy C
|
|
Set if borrow (i.e. if
|
|
.Po Ar r8
|
|
+ carry
|
|
.Pc >
|
|
.Sy A ) .
|
|
.El
|
|
.Ss SBC A,[HL]
|
|
Subtract the byte pointed to by
|
|
.Sy HL
|
|
and the carry flag from
|
|
.Sy A .
|
|
.Pp
|
|
Cycles: 2
|
|
.Pp
|
|
Bytes: 1
|
|
.Pp
|
|
Flags: See
|
|
.Sx SBC A,r8
|
|
.Ss SBC A,n8
|
|
Subtract the value
|
|
.Ar n8
|
|
and the carry flag from
|
|
.Sy A .
|
|
.Pp
|
|
Cycles: 2
|
|
.Pp
|
|
Bytes: 2
|
|
.Pp
|
|
Flags: See
|
|
.Sx SBC A,r8
|
|
.Ss SCF
|
|
Set Carry Flag.
|
|
.Pp
|
|
Cycles: 1
|
|
.Pp
|
|
Bytes: 1
|
|
.Pp
|
|
Flags:
|
|
.Bl -hang -compact
|
|
.It Sy N
|
|
0
|
|
.It Sy H
|
|
0
|
|
.It Sy C
|
|
1
|
|
.El
|
|
.Ss SET u3,r8
|
|
Set bit
|
|
.Ar u3
|
|
in register
|
|
.Ar r8
|
|
to 1.
|
|
Bit 0 is the rightmost one, bit 7 the leftmost one.
|
|
.Pp
|
|
Cycles: 2
|
|
.Pp
|
|
Bytes: 2
|
|
.Pp
|
|
Flags: None affected.
|
|
.Ss SET u3,[HL]
|
|
Set bit
|
|
.Ar u3
|
|
in the byte pointed by
|
|
.Sy HL
|
|
to 1.
|
|
Bit 0 is the rightmost one, bit 7 the leftmost one.
|
|
.Pp
|
|
Cycles: 4
|
|
.Pp
|
|
Bytes: 2
|
|
.Pp
|
|
Flags: None affected.
|
|
.Ss SLA r8
|
|
Shift Left Arithmetically register
|
|
.Ar r8 .
|
|
.Bd -literal
|
|
┏━ Flags ━┓ ┏━━━━━━━ r8 ━━━━━━┓
|
|
┃ C ←╂─╂─ b7 ← ... ← b0 ←╂─ 0
|
|
┗━━━━━━━━━┛ ┗━━━━━━━━━━━━━━━━━┛
|
|
.Ed
|
|
.Pp
|
|
Cycles: 2
|
|
.Pp
|
|
Bytes: 2
|
|
.Pp
|
|
Flags:
|
|
.Bl -hang -compact
|
|
.It Sy Z
|
|
Set if result is 0.
|
|
.It Sy N
|
|
0
|
|
.It Sy H
|
|
0
|
|
.It Sy C
|
|
Set according to result.
|
|
.El
|
|
.Ss SLA [HL]
|
|
Shift Left Arithmetically the byte pointed to by
|
|
.Sy HL .
|
|
.Bd -literal
|
|
┏━ Flags ━┓ ┏━━━━━━ [HL] ━━━━━┓
|
|
┃ C ←╂─╂─ b7 ← ... ← b0 ←╂─ 0
|
|
┗━━━━━━━━━┛ ┗━━━━━━━━━━━━━━━━━┛
|
|
.Ed
|
|
.Pp
|
|
Cycles: 4
|
|
.Pp
|
|
Bytes: 2
|
|
.Pp
|
|
Flags: See
|
|
.Sx SLA r8
|
|
.Ss SRA r8
|
|
Shift Right Arithmetically register
|
|
.Ar r8
|
|
.Pq bit 7 of Ar r8 No is unchanged .
|
|
.Bd -literal
|
|
┏━━━━━━ r8 ━━━━━━┓ ┏━ Flags ━┓
|
|
┃ b7 → ... → b0 ─╂─╂→ C ┃
|
|
┗━━━━━━━━━━━━━━━━┛ ┗━━━━━━━━━┛
|
|
.Ed
|
|
.Pp
|
|
Cycles: 2
|
|
.Pp
|
|
Bytes: 2
|
|
.Pp
|
|
Flags:
|
|
.Bl -hang -compact
|
|
.It Sy Z
|
|
Set if result is 0.
|
|
.It Sy N
|
|
0
|
|
.It Sy H
|
|
0
|
|
.It Sy C
|
|
Set according to result.
|
|
.El
|
|
.Ss SRA [HL]
|
|
Shift Right Arithmetically the byte pointed to by
|
|
.Sy HL
|
|
.Pq bit 7 of the byte pointed to by Sy HL No is unchanged .
|
|
.Bd -literal
|
|
┏━━━━━ [HL] ━━━━━┓ ┏━ Flags ━┓
|
|
┃ b7 → ... → b0 ─╂─╂→ C ┃
|
|
┗━━━━━━━━━━━━━━━━┛ ┗━━━━━━━━━┛
|
|
.Ed
|
|
.Pp
|
|
Cycles: 4
|
|
.Pp
|
|
Bytes: 2
|
|
.Pp
|
|
Flags: See
|
|
.Sx SRA r8
|
|
.Ss SRL r8
|
|
Shift Right Logically register
|
|
.Ar r8 .
|
|
.Bd -literal
|
|
┏━━━━━━━ r8 ━━━━━━┓ ┏━ Flags ━┓
|
|
0 ─╂→ b7 → ... → b0 ─╂─╂→ C ┃
|
|
┗━━━━━━━━━━━━━━━━━┛ ┗━━━━━━━━━┛
|
|
.Ed
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|
.Pp
|
|
Cycles: 2
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|
.Pp
|
|
Bytes: 2
|
|
.Pp
|
|
Flags:
|
|
.Bl -hang -compact
|
|
.It Sy Z
|
|
Set if result is 0.
|
|
.It Sy N
|
|
0
|
|
.It Sy H
|
|
0
|
|
.It Sy C
|
|
Set according to result.
|
|
.El
|
|
.Ss SRL [HL]
|
|
Shift Right Logically the byte pointed to by
|
|
.Sy HL .
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|
.Bd -literal
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|
┏━━━━━━ [HL] ━━━━━┓ ┏━ Flags ━┓
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|
0 ─╂→ b7 → ... → b0 ─╂─╂→ C ┃
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|
┗━━━━━━━━━━━━━━━━━┛ ┗━━━━━━━━━┛
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|
.Ed
|
|
.Pp
|
|
Cycles: 4
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|
.Pp
|
|
Bytes: 2
|
|
.Pp
|
|
Flags: See
|
|
.Sx SRL r8
|
|
.Ss STOP
|
|
Enter CPU very low power mode.
|
|
Also used to switch between double and normal speed CPU modes in GBC.
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|
.Pp
|
|
Cycles: -
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|
.Pp
|
|
Bytes: 2
|
|
.Pp
|
|
Flags: None affected.
|
|
.Ss SUB A,r8
|
|
Subtract the value in
|
|
.Ar r8
|
|
from
|
|
.Sy A .
|
|
.Pp
|
|
Cycles: 1
|
|
.Pp
|
|
Bytes: 1
|
|
.Pp
|
|
Flags:
|
|
.Bl -hang -compact
|
|
.It Sy Z
|
|
Set if result is 0.
|
|
.It Sy N
|
|
1
|
|
.It Sy H
|
|
Set if borrow from bit 4.
|
|
.It Sy C
|
|
Set if borrow (set if
|
|
.Ar r8
|
|
>
|
|
.Sy A ) .
|
|
.El
|
|
.Ss SUB A,[HL]
|
|
Subtract the byte pointed to by
|
|
.Sy HL
|
|
from
|
|
.Sy A .
|
|
.Pp
|
|
Cycles: 2
|
|
.Pp
|
|
Bytes: 1
|
|
.Pp
|
|
Flags: See
|
|
.Sx SUB A,r8
|
|
.Ss SUB A,n8
|
|
Subtract the value
|
|
.Ar n8
|
|
from
|
|
.Sy A .
|
|
.Pp
|
|
Cycles: 2
|
|
.Pp
|
|
Bytes: 2
|
|
.Pp
|
|
Flags: See
|
|
.Sx SUB A,r8
|
|
.Ss SWAP r8
|
|
Swap the upper 4 bits in register
|
|
.Ar r8
|
|
and the lower 4 ones.
|
|
.Pp
|
|
Cycles: 2
|
|
.Pp
|
|
Bytes: 2
|
|
.Pp
|
|
Flags:
|
|
.Bl -hang -compact
|
|
.It Sy Z
|
|
Set if result is 0.
|
|
.It Sy N
|
|
0
|
|
.It Sy H
|
|
0
|
|
.It Sy C
|
|
0
|
|
.El
|
|
.Ss SWAP [HL]
|
|
Swap the upper 4 bits in the byte pointed by
|
|
.Sy HL
|
|
and the lower 4 ones.
|
|
.Pp
|
|
Cycles: 4
|
|
.Pp
|
|
Bytes: 2
|
|
.Pp
|
|
Flags: See
|
|
.Sx SWAP r8
|
|
.Ss XOR A,r8
|
|
Bitwise XOR between the value in
|
|
.Ar r8
|
|
and
|
|
.Sy A .
|
|
.Pp
|
|
Cycles: 1
|
|
.Pp
|
|
Bytes: 1
|
|
.Pp
|
|
Flags:
|
|
.Bl -hang -compact
|
|
.It Sy Z
|
|
Set if result is 0.
|
|
.It Sy N
|
|
0
|
|
.It Sy H
|
|
0
|
|
.It Sy C
|
|
0
|
|
.El
|
|
.Ss XOR A,[HL]
|
|
Bitwise XOR between the byte pointed to by
|
|
.Sy HL
|
|
and
|
|
.Sy A .
|
|
.Pp
|
|
Cycles: 2
|
|
.Pp
|
|
Bytes: 1
|
|
.Pp
|
|
Flags: See
|
|
.Sx XOR A,r8
|
|
.Ss XOR A,n8
|
|
Bitwise XOR between the value in
|
|
.Ar n8
|
|
and
|
|
.Sy A .
|
|
.Pp
|
|
Cycles: 2
|
|
.Pp
|
|
Bytes: 2
|
|
.Pp
|
|
Flags: See
|
|
.Sx XOR A,r8
|
|
.Sh SEE ALSO
|
|
.Xr rgbasm 1 ,
|
|
.Xr rgbds 7
|
|
.Sh HISTORY
|
|
.Nm rgbds
|
|
was originally written by Carsten S\(/orensen as part of the ASMotor package,
|
|
and was later packaged in RGBDS by Justin Lloyd.
|
|
It is now maintained by a number of contributors at
|
|
.Lk https://github.com/gbdev/rgbds .
|