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chore: add unit tests for iw4 techsets
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#include "Game/IW4/Techset/VertexDeclCompilerIW4.h"
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#include "Game/IW4/IW4.h"
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#include "Utils/MemoryManager.h"
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#include <catch2/catch_test_macros.hpp>
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using namespace IW4;
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using namespace Catch;
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using namespace std::literals;
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TEST_CASE("VertexDeclCompilerIW4", "[iw4][techset][compiler]")
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{
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Zone zone("MockZone", 0, GameId::IW4, GamePlatform::PC);
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zone.Register();
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MemoryManager memory;
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AssetCreatorCollection creatorCollection(zone);
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IgnoredAssetLookup ignoredAssetLookup;
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AssetCreationContext context(zone, &creatorCollection, &ignoredAssetLookup);
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auto loader = techset::CreateVertexDeclCompilerIW4(memory);
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SECTION("Can create simple vertex decl")
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{
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auto result = loader->CreateAsset("pp", context);
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REQUIRE(result.HasBeenSuccessful());
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const auto* assetInfo = reinterpret_cast<XAssetInfo<MaterialVertexDeclaration>*>(result.GetAssetInfo());
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const auto* decl = assetInfo->Asset();
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CHECK(decl->name == "pp"s);
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CHECK(decl->hasOptionalSource == false);
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REQUIRE(decl->streamCount == 1);
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CHECK(decl->routing.data[0].source == STREAM_SRC_POSITION);
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CHECK(decl->routing.data[0].dest == STREAM_DST_POSITION);
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}
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SECTION("Can create advanced vertex decl")
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{
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auto result = loader->CreateAsset("pdcc1tt7t1t1n1n", context);
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REQUIRE(result.HasBeenSuccessful());
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const auto* assetInfo = reinterpret_cast<XAssetInfo<MaterialVertexDeclaration>*>(result.GetAssetInfo());
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const auto* decl = assetInfo->Asset();
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CHECK(decl->name == "pdcc1tt7t1t1n1n"s);
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CHECK(decl->hasOptionalSource == true);
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REQUIRE(decl->streamCount == 5);
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CHECK(decl->routing.data[0].source == STREAM_SRC_POSITION);
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CHECK(decl->routing.data[0].dest == STREAM_DST_DEPTH);
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CHECK(decl->routing.data[1].source == STREAM_SRC_COLOR);
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CHECK(decl->routing.data[1].dest == STREAM_DST_COLOR_1);
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CHECK(decl->routing.data[2].source == STREAM_SRC_TANGENT);
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CHECK(decl->routing.data[2].dest == STREAM_DST_TEXCOORD_7);
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CHECK(decl->routing.data[3].source == STREAM_SRC_TEXCOORD_1);
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CHECK(decl->routing.data[3].dest == STREAM_DST_TEXCOORD_1);
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CHECK(decl->routing.data[4].source == STREAM_SRC_NORMAL_TRANSFORM_1);
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CHECK(decl->routing.data[4].dest == STREAM_DST_NORMAL);
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}
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}
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